1. Field of the Invention
The present invention relates to a chopper type DC-DC converter for converting primary voltage into secondary voltage by stepping up and stepping down the primary voltage.
2. Description of Related Art
For a recent portable device, a battery such as a lithium ion battery or a dry cell battery is used. Such battery has a wide range of battery voltage. For example, battery voltage of one lithium ion battery cell has a value in a range from about 2.7 V to about 4.2 V, and battery voltage of two dry cell batteries has a value in a range from 1.8 V to 3.6 V. On the other hand, a device driven by a battery often requires voltage at a specific value within the range of battery voltage of the battery, such as 3.3 V or 2.5 V. In this case, if the battery is fully charged, the battery voltage is stepped down by a step down circuit to the required voltage, and then supplied to the device. On the other hand, if the remaining battery level of the battery is low and the battery voltage is lower than the required voltage of the device, the battery voltage is stepped up to the required voltage, and then supplied to the device. In order to step up and step down battery voltage, a step-up and step-down DC-DC converter is used. As such DC-DC converter, a chopper type step-up and step-down DC-DC converter is widely used from the perspectives of a simple circuit configuration and an advantage in miniaturization.
The chopper type DC-DC converter requires improvement in voltage conversion efficiency. It is required to improve the voltage conversion efficiency without having a circuit configuration complicated and without deteriorating response of an entire system.
FIG. 1 is a circuit diagram showing schematically a typical chopper type step-up and set-down DC-DC converter. The DC-DC converter includes a step-up circuit, a step-down circuit, a comparator 109, an error amplifier 110, a triangular wave generating circuit 111, and a target voltage generating source 112. The step-down circuit includes a switch 103, a reactor 104, and a diode 106. A primary voltage 101 is supplied to an input side of the switch 103. The reactor 104 is connected to an output side of the switch 103. The diode 106 is provided to prevent backflow. In the step-down circuit, by switching the switch 103, energy stored in the reactor 104 is released as a stepped-down voltage. The step-up circuit includes the reactor 104, a switch 105, a diode 107, and a capacitor 108. The reactor 104 is shared by the step-up circuit and the step-down circuit. By switching the switch 105, energy stored in the capacitor 108 is released as a stepped-up voltage. The voltage outputted from the step-up circuit is outputted outside as a secondary voltage 102. The switching of the switches (103 and 105) of the step-up and step-down circuits is performed based on a signal supplied from the comparator 109. The comparator 109 compares an error signal supplied from the error amplifier 110 with a comparative wave (triangular wave) supplied from the triangular wave generating circuit 111, and switches the switches 103 and 105 based on a result of the comparison.
In the DC-DC converter shown in FIG. 1, the switches of the step-up and step-down circuits are switched at the same timing without exception. Accordingly, the step-up and step-down circuits are simultaneously operated, so that energy loss is large, and therefore voltage conversion efficiency is very poor.
On the other hand, Japanese Examined Utility Model Application Publication (JU-Y-Heisei 07-027831) discloses a DC-DC converter. FIG. 2 is a circuit diagram of the DC-DC converter. The DC-DC converter includes a first comparator 221 for switching a step-down transistor 212 as a switch of a step-down circuit and a second comparator 222 for switching a step-up transistor 217 as a switch of a step-up circuit. In the DC-DC converter, an error signal 224S is supplied to a negative input terminal of the first comparator 221. On the other hand, a positive input terminal of the second comparator 222 is supplied with a level-shifted error signal 224S through a level shift circuit. A positive input terminal of the first comparator 221 and a negative input terminal of the second comparator 222 are supplied with a triangular wave generated by an oscillator 223 as a comparative wave. Japanese Examined Utility Model Application Publication (JU-Y-Heisei 07-027831) describes that the switching of only one of the step-up and step-down transistors 217 and 212 is controlled, and therefore switching loss can be reduced.
Japanese Laid Open Patent Application (JP-P2000-166223A) discloses that a synchronizing clock is supplied to a sawtooth wave generating circuit and a level shift circuit to synchronize the waveforms of comparative waves (sawtooth waves) respectively supplied to a step-up side comparator and a step-down side comparator with each other. FIG. 3 is a circuit diagram of a DC-DC converter disclosed in Japanese Laid Open Patent Application (JP-P2000-166223A). As shown in FIG. 3, a positive input terminal of the step-down side comparator is supplied with the sawtooth wave from the sawtooth wave generating circuit. A positive input terminal of the step-down side comparator is supplied with the sawtooth wave shifted-up by the level shift circuit. Minus input terminals of the step-up side and step-down side comparators are supplied with an error voltage from an error amplifier. The level shift circuit and the sawtooth wave generating circuit are supplied with a current source and the synchronizing clock, and thus waveforms of the sawtooth waves supplied to the step-up side and step-down side comparators are same in shape but different in level. In general, a signal having passed through a level shift circuit has an influence due to a phase difference. Accordingly, there is concern that a ratio (duty ratio) between a time period in which a comparator outputs a high level and a time period in which the comparator outputs a low level deviates from an ideal ratio due to the phase difference. However, according to Japanese Laid Open Patent Application (JP-P2000-166223A), the waveforms of the sawtooth waves are synchronized each other based on the synchronizing clock, and thus the duty ratio between signals (Dup and Dup′) outputted by the comparators is unchanged as shown in FIG. 4. Note that Ddn in FIG. 4 represents an output of the step-down side comparator.
In addition, Japanese Laid Open Patent Application (JP-A-Showa 63-103668) discloses an art concerning to a comparative wave supplied to a comparator of a push-pull type step-up and step-down converter.
The present inventor has recognized as follows.
As described in the above Japanese Examined Utility Model Application Publication (JU-Y-Heisei 07-027831) and Japanese Laid Open Patent Application (JP-P2000-166223A), if both the step-up and step-down comparators are provided separately and the error signal or comparative wave supplied to one of the comparators is level-shifted, only one of the step-down and step-up circuits can be driven depending on the level of the error signal, and therefore energy loss can be suppressed.
However, in a case of using the level shift circuit, there is a phase difference between an input signal to the level shift circuit and an output signal therefrom due to gain and offset of the level shift circuit. For this reason, a phase correction circuit is required to compensate both the phase difference due to the level shift circuit and a phase difference for the error signal due to a feedback loop. This causes problems that a circuit configuration is complicated and response of an entire system is deteriorated.
Also, it is difficult to adequately control a level shift amount in the level shift circuit. Accordingly, in practice, it is necessary to partially overlap a range in which the step-up circuit is driven and a range in which the step-down circuit is driven to secure a margin. For example, if the sawtooth wave as the comparative wave is shifted up and then supplied to the step-up side comparator, as shown in FIG. 5, amplitudes of a first sawtooth wave as the sawtooth wave supplied to the step-up side comparator and a second sawtooth wave as the sawtooth wave supplied to the step-down side comparator are partially crossed each other to secure a margin. The margin is indicated as a target cross margin. If the level of the error signal falls within range of voltage of the crossing portion, both of the step-up and step-down circuits will be driven simultaneously, resulting in poor voltage conversion efficiency.
Furthermore, if a high frequency wave is used as the comparative wave, a charging and discharging switching circuit in the oscillator for generating the comparative wave will have a delay time, resulting in an increase in amplitude of the comparative wave. The reason will be described referring to FIG. 6. FIG. 6 is a circuit diagram of the sawtooth wave generating circuit. The sawtooth wave generating circuit includes a comparator, a charging and discharging circuit, and a capacitor. The comparator detects a voltage at an output terminal, and controls the charging and discharging circuit to be in one of charging and discharging modes such that the output terminal voltage falls within a range between a lower threshold and an upper threshold. The lower and upper thresholds are determined by a threshold voltage inputted to a negative input terminal of the comparator.
Specifically, if the charging and discharging circuit is set in the charging mode, a constant current is supplied to the capacitor, and an output side voltage is increased at a constant rate. When the output side voltage reaches the upper threshold, the comparator set the charging and discharging circuit in the discharging mode. When the charging and discharging circuit is set in the discharging mode, the capacitor is discharged via the charging and discharging circuit, and the output side voltage is decreased. When the output side voltage reaches the lower threshold, the comparator sets the charging and discharging circuit to be in the charging mode again. Thus, the sawtooth wave is generated. By increasing a current flowing into the capacitor at the charging mode, the frequency of the sawtooth wave is increased. However, if the frequency is increased, the timing at which the comparator switches the charging and discharging circuit between the charging and discharging modes is delayed from the timing at which the output side voltage reaches the threshold. For this reason, the capacitor is excessively charged or discharged, and therefore the output side voltage exceeds the threshold value. Consequently, the amplitude of the comparative wave is increased. That is, as shown in FIG. 5, an actual sawtooth wave indicated by a dashed line is deviated from a target sawtooth wave indicated by a solid line, and therefore an actual range of the cross voltage is wider than a range of the target cross voltage. For this reason, the range in which both of the step-up and step-down circuits are driven is extended.